SRCPERIPHERAL=SOURCE_EQ_SPIFI, E=CHANNEL_DISABLED_, H=ENABLE_DMA_REQUESTS_, FLOWCNTRL=MEMORY_TO_MEMORY, DESTPERIPHERAL=DESTINATION_EQ_SPIFI
DMA Channel Configuration Register
| E | Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. 0 (CHANNEL_DISABLED_): Channel disabled. 1 (CHANNEL_ENABLED_): Channel enabled. |
| SRCPERIPHERAL | Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details. 0 (SOURCE_EQ_SPIFI): Source = SPIFI 1 (SOURCE_EQ_TIMER_0_MAT): Source = Timer 0 match 0/UART0 transmit 2 (SOURCE_EQ_TIMER_0_MAT): Source = Timer 0 match 1/UART0 receive 3 (SOURCE_EQ_TIMER_1_MAT): Source = Timer 1 match 0/UART1 transmit 4 (SOURCE_EQ_TIMER_1_MAT): Source = Timer 1 match 1/UART 1 receive 5 (SOURCE_EQ_TIMER_2_MAT): Source = Timer 2 match 0/UART 2 transmit 6 (SOURCE_EQ_TIMER_2_MAT): Source = Timer 2 match 1/UART 2 receive 7 (SOURCE_EQ_TIMER_3_MAT): Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0 8 (SOURCE_EQ_TIMER_3_MAT): Source = Timer 3 match 1/UART3 receive/SCT DMA request 1 9 (SOURCE_EQ_SSP0_RECEIV): Source = SSP0 receive/I2S channel 0 10 (SOURCE_EQ_SSP0_TRANSM): Source = SSP0 transmit/I2S channel 1 11 (SOURCE_EQ_SSP1_RECEIV): Source = SSP1 receive 12 (SOURCE_EQ_SSP1_TRANSM): Source = SSP1 transmit 13 (SOURCE_EQ_ADC0): Source = ADC0 14 (SOURCE_EQ_ADC1): Source = ADC1 15 (SOURCE_EQ_DAC): Source = DAC |
| DESTPERIPHERAL | Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details. 0 (DESTINATION_EQ_SPIFI): Destination = SPIFI 1 (DESTINATION_EQ_TIMER_): Destination = Timer 0 match 0/UART0 transmit 2 (DESTINATION_EQ_TIMER_): Destination = Timer 0 match 1/UART0 receive 3 (DESTINATION_EQ_TIMER_): Destination = Timer 1 match 0/UART1 transmit 4 (DESTINATION_EQ_TIMER_): Destination = Timer 1 match 1/UART 1 receive 5 (DESTINATION_EQ_TIMER_): Destination = Timer 2 match 0/UART 2 transmit 6 (DESTINATION_EQ_TIMER_): Destination = Timer 2 match 1/UART 2 receive 7 (DESTINATION_EQ_TIMER_): Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0 8 (DESTINATION_EQ_TIMER_): Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1 9 (DESTINATION_EQ_SSP0_R): Destination = SSP0 receive/I2S channel 0 10 (DESTINATION_EQ_SSP0_T): Destination = SSP0 transmit/I2S channel 1 11 (DESTINATION_EQ_SSP1_R): Destination = SSP1 receive 12 (DESTINATION_EQ_SSP1_T): Destination = SSP1 transmit 13 (DESTINATION_EQ_ADC0): Destination = ADC0 14 (DESTINATION_EQ_ADC1): Destination = ADC1 15 (DESTINATION_EQ_DAC): Destination = DAC |
| FLOWCNTRL | Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field. 0 (MEMORY_TO_MEMORY): Memory to memory (DMA control) 1 (MEMORY_TO_PERIPHERAL): Memory to peripheral (DMA control) 2 (PERIPHERAL_TO_MEMORY): Peripheral to memory (DMA control) 3 (SOURCE_PERIPHERAL_TO): Source peripheral to destination peripheral (DMA control) 4 (SOURCE_PERIPHERAL_TO): Source peripheral to destination peripheral (destination control) 5 (MEMORY_TO_PERIPHERAL): Memory to peripheral (peripheral control) 6 (PERIPHERAL_TO_MEMORY): Peripheral to memory (peripheral control) 7 (SOURCE_PERIPHERAL_TO): Source peripheral to destination peripheral (source control) |
| IE | Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. |
| ITC | Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. |
| L | Lock. When set, this bit enables locked transfers. |
| A | Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. |
| H | Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. 0 (ENABLE_DMA_REQUESTS_): Enable DMA requests. 1 (IGNORE_FURTHER_SOURC): Ignore further source DMA requests. |
| RESERVED | Reserved, do not modify, masked on read. |